Mixed signal integrated circuits provide analog and digital signal processing capabilities on single chip structures. The capability of miniaturizing digital and analog devices on a single mixed-signal IC has made a considerable economic impact in the video and radio frequency (RF) communications markets.
Like conventional digital IC's, mixed-signal IC's typically undergo extensive tests to verify acceptable operation. Generally, the tests are carried out on each device under test (DUT) by an automatic test system commonly referred to as a "tester". The tester generally checks out each DUT by applying digital patterns or vectors to selected DUT pins to simulate actual or expected operating conditions under a variety of scenarios. The outputs generated by the IC, in response to the test input signals, are captured by the tester and compared against expected outputs to determine whether any faults exist.
For digital IC's, the vectors are typically programmed and executed entirely in the digital domain. In contrast, mixed-signal devices require test inputs from not only digital patterns, but also analog waveforms. In order to conduct repetitive and deterministic testing procedures, the digital signals, analog signals and commands or opcode patterns must be applied to the mixed signal device in a predictable manner. Generally, this involves implementing an analog signal generator or clock having a deterministic phase relationship to the digital clock.
An important reason for requiring the predictable phase relationship between the analog and digital clock involves opcode or instruction passing between the digital and analog domains. Typically, the digital and analog waveforms and the associated instruction sets originate from software resident in the digital domain. In order for analog instruments to process commands at the correct timing with respect to the digital clock, the instruction must be "tossed" from the digital to the analog domain appropriately. Thus, the combination of digital timing, analog timing, and respective phases between waveforms must be consistent and predictable from test-to-test.
One proposal for a mixed-signal tester, such as the Catalyst model available from Teradyne Inc., the assignee of the present invention, generates an analog clock through direct-digital-synthesis (DDS) of a high-speed digital clock. DDS techniques for generating analog clocks are well known in the art and generally involve driving a counter with a digital clock, such that the counter incrementally advances a summed value with each subsequent clock period. The count value is referenced to a look-up table or memory for a digital representation of an analog sine wave. The digital representation is then fed through a digital-to-analog converter (DAC) to produce the analog signal. Further conditioning of the analog signal often occurs to form the desired analog clock
To predict the relative phases between the digital master clock and the DDS-generated analog clock, the tester described above drives the DDS module with a 500 MHz digital signal that, in turn, is referenced to a 100 MHz master oscillator. The 500 MHz clock provides five potential rising-edges for generating an analog clock edge within the reference 100 MHz clock period. A processor evaluates the edges to determine which digital edge lies coincident with the analog edge. This information is then fed to an opcode passing mechanism to avoid "tossing" microcode during the 100 MHz period of the digital master oscillator that includes the analog edge.
While this system works well for its intended applications, the implementation of a 500 MHz clock to provide finer resolution in the edge prediction technique presents some problems. First, generating a 500 MHz waveform often uses a combination of lower-speed modules multiplexed and interleaved to create a higher frequency signal. Not only is this often fairly costly in terms of hardware, but the time expended in controlling and maintaining the calibration of such a high-frequency device creates additional costs. In addition, as the speed of operation is increased, creating a 5.times. clock becomes a technical problem which itself limits the range of application of the invention.
What is needed and heretofore unavailable is an analog clock module that provides a cost-effective approach to generate an analog clock from a digital clock and predict the relative phase relationships between the respective clocks. Moreover, the need exists for an analog clock that maintains a relatively stable calibration, and automatically calibrates. Additionally, the need exists for such an analog clock having independent adjustable controls to manipulate the analog clock with respect to the digital clock. The analog clock module of the present invention satisfies these needs.